Ferroelectric polymers have generated a great deal of interest for use in semiconductor devices, especially memory devices, due to its fast polarization reversal in the presence of an electric field and its ability to maintain a polarization state once the electric field is removed. For this reason, ferroelectric polymers are being considered for use in stacked ferroelectric memory arrays. The memory arrays are formed by connecting the metal layers through a series of interlayer vias on a ferroelectric polymer memory die.
There are however, several problems associated with forming the interlayer vias in ferroelectric polymer memories dies. First, in forming the interlayer vias on a ferroelectric polymer die, the vias are patterned on a stack of interlevel dielectric (ILD) layers, which are typically an oxide, and the ferroelectric polymer layer. However, the ferroelectric polymer layer has a different etch rate than the oxide. Additionally, the ferroelectric polymer has a lateral etch rate that is equal to or greater than the vertical etch rate. Therefore, in the process of etching the via pattern, and removing the patterned photoresist, the difference in etch rates in the ferroelectric polymer layer results in a via sidewall that is retrograde from the ILD layer. As a result of the retrograde via sidewall, the next metal layer cannot be easily deposited on the sidewall of the vias, which results in marginal electrical continuity between adjoining metal layers.
Second, the topography of the ferroelectric polymer memory die increases with each additional metallization layers because the vias are not filled with metal and therefore, are not coplanar with the ILD layer. The lack of planarization limits the number of metallization layers and therefore decreases the memory density.
Another problem is that ferroelectric polymer memory dies require low temperature processing, typically below 120 degrees Celsius. This is due to the fact that ferroelectric polymers have a Currie temperature of about 120 degrees Celsius. Therefore, conventional chemical vapor deposition (CVD) processes cannot be used with ferroelectric polymers since the CVD process typically takes place between 300 and 500 degrees Celsius well above the Currie temperature of ferroelectric polymers. Therefore, any attempt use a CVD process to fill the vias will result in the ferroelectric polymer breaking down.
One method to attempt to improve the coverage of the via sidewalls is simply to increase the thickness of the metal layer deposited on the ILD layer, which deposits more metal in the via, thereby improving the sidewall coverage. However, this approach has several drawbacks. First, increasing the thickness of the metal layer deposited increases the overall topography of the ferroelectric polymer and metal stack, which reduces the ability to stack multiple metallization layers on a single die. The limitation occurs because typically, in memory dies, the patterned lines and spaces are about 150 to 250 nanometers in width. To meet these patterning requirements and maintain reasonable process operating windows, the thickness of the metal layer should be less than one thousand angstroms (1000 Å). Increasing the metal layer beyond 1000 Å makes it difficult and therefore, more expensive to effectively pattern the metal layer to the required specifications. Lastly, the metal layer has a different thermal expansion coefficient than the ILD layer. Increasing the thickness of the metal layer may lead to a build up of stresses at the metal-ILD junction, which may cause the oxide layer to delaminate, and render the device useless.